Designer is Actel's powerful physical implementation software tool suite for all Actel FPGAs. After completing design entry and functional verification using Libero IDE tools or your favorite front-end design tools, simply import the resulting netlist into Designer to set timing constraints and performing place-and-route, timing analysis, power analysis, and program file generation.

Designer provides full power optimization and analysis tools for Actel's low-power flash FPGA families, including IGLOO and ProASIC3L, the latest addition to the ProASIC3 family.

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